Tuesday, January 23rd 2018, 8:44am UTC+1

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The last 2 posts

Thursday, January 11th 2018, 9:25am

by SEGGER - Til

Hi Kenny,

OS_EnterInterrupt() disables interrupts with setting BASEPRI register to 0x80 which disables all embOS interrupts.
OS_EnterNestableInterrupt() does not change the BASEPRI register and therefore does not disable interrupts.

Quoted

Are OS_EnterInterrupt and OS_EnterNestableInterrupt effectively the same on Cortex-M?

Yes, they also work with Cortex-M. The macro is not necessary in all embOS ports.
The interrupt handler could be preempted before OS_EnterInterrupt() is actually called but that's no problem for embOS and usually no problem for the application.

Best regards,
Til

Thursday, January 11th 2018, 4:00am

by Kenny

OS_EnterInterrupt/OS_EnterNestableInterrupt on Cortex-M

I have two timer interrupts which both use OS_Enter/OS_LeaveInterrupt. One has a higher priority than the other. Both are at lower priorities (higher values) than the fast interrupt. My understanding is that these routines disable interrupts that are not so-called fast interrupt. Using a scope I set two GPIOs high when entering these routines and low when leaving. I can clearly see the lower interrupt preempted by that with the higher priority.

From the Cortex-M EMBOS manual:

Quoted

OS_EnterInterrupt() has to be used as prolog function, when the interrupt handler should not be preempted by any other interrupt handler that runs on a priority below the fast interrupt priority. An interrupt handler that starts with OS_EnterInterrupt() has to end with the epilog function OS_LeaveInterrupt().
From the RTOS header files where the macros are defined:

Quoted



#define OS_ENABLE_INTS_SAVE_IPL() // Not required with Cortex-M, avoid call of OS_EI()
Are OS_EnterInterrupt and OS_EnterNestableInterrupt effectively the same on Cortex-M? Why is my interrupt above being preempted?