Sunday, May 20th 2018, 12:12pm UTC+2

You are not logged in.

  • Login
  • Register

Search results

Search results 1-20 of 271.

Wednesday, May 16th 2018, 1:39pm

Author: SEGGER - Til

embos ERROR 166

Could you please contact us per our embOS support email address and share your company name, embOS license number and your project with us? I think that makes it easier. Thanks, Til

Wednesday, May 16th 2018, 1:08pm

Author: SEGGER - Til

embos ERROR 166

Correct, the STM32F303 has 4 priority bits implemented. The actual priority register has 8 bits and the 4 lower bits are always zero. That means you can have the priorities 0x00, 0x10, 0x20...0xF0. Interrupt priorities below 0x80 arre zero latency interrupt priorities and anything else is an embOS interrupt priority. Please have in mind with Cortex-M lower value means higher priority, e.g. 0x00 ist the highest interrupt priority. Best regards, Til

Wednesday, May 16th 2018, 12:10pm

Author: SEGGER - Til

embos ERROR 166

Quoted // Set the Interrupt Priority and Sub-Priority I_STM_NVIC_SetPriority(TIM3_IRQn, 04, 00); Most likely that causes the problem but depends on how much interrupt priority bits are usable in your actual device. Could you please have a look in the CPU/Compiler specific embOS manual in chapter "Interrupts". Basically embOS splits the Cortex-M interrupt priorities in two parts: embOS interrupt priorities and zero latency interrupt priorities. embOS API can be called from interrupts with embOS ...

Wednesday, May 16th 2018, 11:53am

Author: SEGGER - Til

embos ERROR 166

Hi, are you using a valid embOS license or an embOS trial version? I am not sure if I understood your code snippet correctly. 1. Where do you call OS_SignalEvent()? 2. What is the last function before OS_Error() in your call stack? Basically this error message tells you that an embOS API was called from an invalid CPU state. That could e.g. happen with Cortex-M when your ISR routine used an invalid interrupt priority. I guess you are not using embOS ARM IAR but embOS Cortex-M IAR, correct? Best ...

Wednesday, May 16th 2018, 9:01am

Author: SEGGER - Til

heap in external RAM

I think that question is more related to Rowley Crossworks than embOS. Did you change the linker file accordingly? Could you please share that with us? I will also check whether we can provide a sample project or linker file. Btw. As you are still in support please don't hesitate to contact us with the embOS support email address. Best regards, Til

Tuesday, March 27th 2018, 9:45am

Author: SEGGER - Til

OS_Delayus() not fast enough

Hi Lior, did you make any changes to the board support package, especially OS_GetTime_Cycles()? I'll check if we have the same device/evalboard here and give it a try. But I am pretty sure it should work as expected. Best regards, Til

Thursday, March 1st 2018, 4:35pm

Author: SEGGER - Til

[SOLVED] semaphore already created?

Hi Axel, no, there is unfortunately no easy way and I don't think you example will work like that since you have only declared a pointer but not the variable itself. Usually it would be something like: OS_RSEMA sema; OS_CreateRSema(&sema); But &sema has also a valid value before OS_CreateRSema() . With the debug build of embOS you could check sema.Id which gets a valid value when the semaphore is created. But this Id member is only available in embOS debug builds. Best regards, Til

Tuesday, February 13th 2018, 8:02am

Author: SEGGER - Til

[SOLVED] USART DMA not receving data with embOS

Hello Santhosh, I don't know which device you are actually using but it should work the same with embOS. embOS does not have any influence on your DMA or Uart. IRQ interrupts are handled via embOS with a low level interrupt handler in assembler and a high level interrupt handler in your RTOSInit.c. Could you please check your MMU table in the RTOSInit.c? It defines which memory regions are cached. That could be an issue because the DMA writes directly to the memory and you are maybe just reading...

Thursday, January 11th 2018, 9:25am

Author: SEGGER - Til

[SOLVED] OS_EnterInterrupt/OS_EnterNestableInterrupt on Cortex-M

Hi Kenny, OS_EnterInterrupt() disables interrupts with setting BASEPRI register to 0x80 which disables all embOS interrupts. OS_EnterNestableInterrupt() does not change the BASEPRI register and therefore does not disable interrupts. Quoted Are OS_EnterInterrupt and OS_EnterNestableInterrupt effectively the same on Cortex-M? Yes, they also work with Cortex-M. The macro is not necessary in all embOS ports. The interrupt handler could be preempted before OS_EnterInterrupt() is actually called but t...

Thursday, December 21st 2017, 1:39pm

Author: SEGGER - Til

embOS Tickless Support

Hi Ivan, do you need an application note for embOS tickless mode or regarding the specific EFR32 low power moders? Please find the embOS tickless mode application note here: https://www.segger.com/downloads/application-notes/AN01002 Best regards, Til

Friday, November 17th 2017, 10:05am

Author: SEGGER - Til

[SOLVED] CMSIS-rtos interface to embOS

Hello Marek, Quoted Is it possible to get the CMSIS-rtos solution as support from you? Yes, sure. Are you looking for CMSIS-RTOS v1 or CMSIS-RTOS v2? http://arm-software.github.io/CMSIS_5/RTOS/html/index.html http://arm-software.github.io/CMSIS_5/RTOS2/html/index.html We have support for both versions but they are sold separately. Quoted Is your solution compatible only with some specific embOS version (oldest which we are using is 3.88)? CMSIS RTOS v1 layer can be used with any embOS version. C...

Friday, November 3rd 2017, 11:56am

Author: SEGGER - Til

[SOLVED] Interrupt-stack switching on RL78 for zero-latency interrupts

Hi Markus, Quoted In the RL78 embOS manual it is described that zero-latency interrupts must not execute any embOS function. Therefore it is not allowed to call the functions OS_EnterIntStack resp. OS_LeaveIntStack, is that correct? Yes, that's correct. Quoted This means that all tasks must preserve some space on their stack for the zero-latency interrupts because the switching is not allowed. Depending on the zero-latency ISR implementation this can afford large stacks for all tasks... Unfortun...

Sunday, October 29th 2017, 2:31pm

Author: SEGGER - Til

[SOLVED] Change CPU frequency after OS_Start();

Hello Kari, if you just want to change the CPU frequency at run-time you can do so with no major impact to the OS. You must just ensure the system tick interrupt still occurs at the same period by e.g. adjusting the timer clock settings or timer reload/compare value. Best regards, Til

Monday, October 23rd 2017, 4:33pm

Author: SEGGER - Til

[SOLVED] OS_WD_Config(): How to configure pfTriggerFunc?

Quoted If I'm correct, my watchdog in Idle loop is efficient for: -> trapped in OS_Error(), -> infinite loops without OS_Delay() consuming all the resource, Yeah, that's it. Usually you don't have the debug code and OS_Error() in your release firmware. Although you can do so, of course! But in that case you could also directly reset your microcontroller in OS_Error().

Monday, October 23rd 2017, 9:52am

Author: SEGGER - Til

[SOLVED] OS_WD_Config(): How to configure pfTriggerFunc?

Dear JLuc, Quoted In my mind, if any task is blocked, the idle loop is not reached anymore and the hardware watchdog is triggered. There could be situations where one task is not running as expected but OS_Idle() still gets executed. Also triggering the watchdog in OS_Idle() only does not help because there could be a task which runs for a long time and therefore you don't reach OS_Idle() on time. I guess you think of situations only where the CPU "stops" in a task and no further code gets execu...

Wednesday, October 18th 2017, 10:19pm

Author: SEGGER - Til

[SOLVED] Queues: queue pointer corruption

Hello Bryan, i am not aware of such an issue but please let me double check tomorrow (I am not in office right now). We will contact you directly by email or phone. I am pretty sure we can solve your issue tomorrow. Quoted This mentions making the buffer size larger than the sum of all messages, but it doesn't state HOW MUCH LARGER. Any clue? The queue data buffer contains the messages and some additional management information. Each message has a message header containing the message size. The ...

Thursday, October 5th 2017, 8:38am

Author: SEGGER - Til

[SOLVED] Will OS_EnterRegion()/OS_LeaveRegion() prevent a software timer from running its handler?

Hi Kenny, Yes, embOS software timer are executed from within the scheduler. Therefore you should keep your critical regions with OS_EnterRegion()/OS_LeaveRegion() as short as possible. Best regards, Til

Wednesday, September 13th 2017, 1:18pm

Author: SEGGER - Til

[SOLVED] Code getting stuck in OS_InitKern_STD

Hi Gautam, I got your email, so we can continue the discussion there. Best regards, Til

Wednesday, September 13th 2017, 11:54am

Author: SEGGER - Til

[SOLVED] Code getting stuck in OS_InitKern_STD

Hi Gautam, do you have an embOS license or are you working with an embOS trial version? You can also contact our embOS support directly per email. Please find the email address in the embOS manual in chapter "Support". OS_InitKern() does not call OS_Delay() at all. I don't see your call to OS_Delay() in your code snippet. Please be aware OS_Delay() can only work after the hardware timer was initialized and interrupts are enabled. This is usually done in OS_InitHW(). If you call OS_Delay() in mai...

Wednesday, July 19th 2017, 3:50pm

Author: SEGGER - Til

[SOLVED] OS_WD_Config(): How to configure pfTriggerFunc?

Hi, from the embOS manual: Quoted pfResetFunc may be used to perform additional operations inside a callback function prior to the reset of the microcontroller. The reset function is optional and gives the chance to react on such a situation. You could e.g. write a message in a log file or set a piece of hardware in safe state before resetting the μC. The basic idea is that one hardware watchdog is not enough for an RTOS with multiple tasks. If you would trigger the hardware watchdog in one task...