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ohnail

Beginner

Date of registration: Feb 9th 2012

Posts: 24

1

Thursday, February 9th 2012, 9:21am

[SOLVED]AM335x support?

Hi Sir,

I have a EVK board named BeagleBone. The cpu is AM3359. I want to debug it by using my J-Link ultra.
I can't find any JTAG information in the reference manual of AM335x.
Could you confirm whether J-Link ultra supports AM335x?
Thanks a lot.


Ohnail
9th Feb. 2012

SEGGER - Alex

Super Moderator

Date of registration: Dec 18th 2007

Posts: 1,516

2

Friday, February 10th 2012, 7:55pm

Hi Ohnail,

We are currently working on the AM335x support.
It is a bit tricky since
a) There is an ICEPick device which needs to be initialized before the core is available
b) Some coresight information in the device does not seem to be correct and needs to be setup manually.

We will post it here as soon as AM335x support is available.


Best regards
Alex

ohnail

Beginner

Date of registration: Feb 9th 2012

Posts: 24

3

Saturday, February 11th 2012, 2:50am

Hi Alex,

Thanks a lot!

I tried to modify the script of AM3517 by myself.
I knew the icepick id of AM3359 is 0x0B94402F and icepick code is 0x1015B3D6. And the arm core is the 12th TAP.
But it looks J-Link can't identify all of the DPs.

I paste the config file of BDI3000. It looks so easy.

Source code

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[INIT]

[TARGET]
CPUTYPE     CORTEX-A8 0xCB141000
CLOCK       1                   ;JTAG clock
POWERUP     2000                ;power-up delay
TRST        PUSHPULL            ;TRST driver type (OPENDRAIN | PUSHPULL)
;RESET	    NONE	        ;Reset signal is not routed to the debug
STARTUP     RESET               ;let boot code setup the system
ENDIAN      LITTLE              ;memory model (LITTLE | BIG)
WAKEUP      100
MEMACCESS   CORE  1             ;memory access via core (8 TCK's access delay)
;MEMACCESS   AHB   1             ;memory access via AHB  (8 TCK's access delay)
STEPMODE    OVER                ;OVER or INTO
VECTOR		CATCH
BREAKMODE   HARD

; Configure ICEPick module to make Cortex-A8 DAP-TAP visible
; Polar family has A8 core on TAP28 which is in Debug TAP linking block 1
SCANINIT    t1:w1000:t0:w1000:  ;toggle TRST,
SCANINIT    ch10:w1000:         ;clock TCK with TMS high and wait
SCANINIT    i6=07:d8=89:i6=02:  ;connect and select router
SCANINIT    d32=81000080:       ;IP control: KeepPowered
SCANINIT    d32=ac002048:       ;TAP12: DebugConnect, ForcePower, ForceActive
SCANINIT    d32=e0002048:       ;Core#0: DebugConnect, ForcePower, ForceActive
SCANINIT    d32=81000081:       ;IP control: KeepPowered, SysReset
SCANINIT    d32=ac002148:       ;enable TAP12
SCANINIT    cl10:i10=ffff       ;clock 10 times in RTI, scan bypass

SCANPRED    1 6                 ;count for ICEPick TAP
SCANSUCC    0 0                 ;no device after Cortex-A8

[HOST]
IP          10.10.10.30
FILE        dump.bin
FORMAT      BIN 0x80000000
LOAD        MANUAL
PROMPT      AM335x-EVM>

[FLASH]

[REGS]
FILE	regOMAP3500.def

This post has been edited 1 times, last edit by "ohnail" (Feb 15th 2012, 1:53am)


ohnail

Beginner

Date of registration: Feb 9th 2012

Posts: 24

4

Saturday, February 11th 2012, 2:54am

My script file

C/C++ Source code

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/*********************************************************************
*               SEGGER MICROCONTROLLER GmbH & Co KG                  *
*       Solutions for real time microcontroller applications         *
**********************************************************************
*                                                                    *
*       (c) 2011  SEGGER Microcontroller GmbH & Co KG                *
*                                                                    *
*       www.segger.com     Support: support@segger.com               *
*                                                                    *
**********************************************************************
----------------------------------------------------------------------
Purpose : J-Link script file for TI AM3359 device.
          By default, only the TI ICEPick is in the JTAG chain
          which means that we have to add the Cortex-A8 by configuring the ICEPick.
          Moreover, the AM3359 also requires to set the DEBGEN signal in order to allow debugging.
---------------------------END-OF-HEADER------------------------------
*/

/*********************************************************************
*
*       _StoreSelDP
*/
void _StoreSelDP(void) {
  JTAG_StoreIR(0xA);  // DPACC command
  JTAG_StoreClocks(1);
}

/*********************************************************************
*
*       _StoreSelAP
*/
void _StoreSelAP(void) {
  JTAG_StoreIR(0xB);  // APACC command
  JTAG_StoreClocks(1);
}

/*********************************************************************
*
*       _StoreTriggerReadAPDPReg
*
*  Function description
*    Triggers a read of an AP or DP register. Depends on the previous command (DPACC / APACC)
*/
int _StoreTriggerReadAPDPReg(unsigned int RegIndex) {
  __int64 v;        // We need 35 bits: 32 data, 2 bit addr, 1 bit RnW
  int BitPosData;
  //
  // Write 35 bits (32 bits data, 2 bits addr, 1 bit RnW)
  //
  v = 0;
  v |= 1;                // 1 indicates read access
  v |= (RegIndex << 1);
  BitPosData = JTAG_StoreDR(v, 35);
  JTAG_StoreClocks(8);
  return BitPosData;
}

/*********************************************************************
*
*       _StoreWriteAPDPReg
*
*  Function description
*    Writes an AP or DP register. Depends on the previous command (DPACC / APACC)
*/
int _StoreWriteAPDPReg(unsigned int RegIndex, __int64 Data) {
  __int64 v;        // We need 35 bits: 32 data, 2 bit addr, 1 bit RnW
  int BitPosData;
  //
  // Write 35 bits (32 bits data, 2 bits addr, 1 bit RnW)
  //
  v = 0;   // 0 indicates write access
  v |= (RegIndex << 1);
  v |= (Data << 3);
  BitPosData = JTAG_StoreDR(v, 35);
  JTAG_StoreClocks(8);
  return BitPosData;
}

/*********************************************************************
*
*       _InitIcePick
*
*  Function description
*    Configures the ICEPick so that the CPU core also becomes
*    visible in the JTAG chain.
*/
void _InitIcePick(void) {
  unsigned int aDevice[2];
  int BitPos;
  int v;
  int ICEPickCode;
  int ICEPickIdCode;
  int DPIdCode;
  int i;
  int Speed;

  Report("J-Link script: Init ICEPick begin!");
  JTAG_Reset();                           // Perform TAP reset and J-Link JTAG auto-detection
  if (JTAG_TotalIRLen != 6) {
    MessageBox1("Can not find ICE-Pick (IRLen mismatch), JTAG_TotalIRLen = ", JTAG_TotalIRLen);
  }
  JTAG_DRPre  = 0;
  JTAG_DRPost = 0;
  JTAG_IRPre  = 0;
  JTAG_IRPost = 0;
  JTAG_IRLen  = 6;
  Speed = JTAG_Speed;
  JTAG_Speed = 50;
  //
  // Check IDCODE of ICEPick (do not confuse with ICEPICKCODE or IDCODE of JTAG-DP)
  //
  JTAG_WriteIR(4);   // IDCODE instruction for ICEPick device
  BitPos = JTAG_WriteDR(0x00000000, 32);
  ICEPickIdCode = JTAG_GetU32(BitPos);      // 0x0B94402F

  if ((ICEPickIdCode & 0x0FFFFFFF) != 0x0B94402F) {                                                       // highest nibble holds version information, so it can not be used for verification.
    MessageBox1("Can not find ICE-Pick (IDCODE mismatch). Expected 0x0B94402F, found: ", ICEPickIdCode);
    return 1;
  }
  //
  // Read ICEPICKCODE
  //
  JTAG_WriteIR(5);
  BitPos = JTAG_WriteDR(0x00000000, 32);
  ICEPickCode = JTAG_GetU32(BitPos);        // 0x1015B3D6
 
  if ((ICEPickCode & 0x0000FFF0) != 0x0000B3D0) {
    MessageBox1("Connected module is not an ICEPick Module (ICEPICKCODE mismatch), found: ", ICEPickCode);
    return 1;
  }
  //
  // Put ARM core in JTAG chain
  //  
  JTAG_WriteIR(7);         // CONNECT
  JTAG_WriteDR(0x89, 8);   // The ICEPick documentation (SPRUE64, 2.6 CONNECT instruction: Accessing the debug connect register). Bit 7 set means: Write debug connect register. We write 0x9 to the debug connect register which is the debug connect key.
  JTAG_WriteIR(2);         // ROUTER (Accessing the mapped registers)
  v = 0
    | (1 << 31)            // Write mapped register
    | (0x2C << 24)         // SDTAP12 register
    | (1 << 13)            // Debug connect
    | (1 << 8)             // TAP select
    | (1 << 3)             // Force active
    ;
  JTAG_WriteDR(v, 32);     // v = 0xAC002108
  JTAG_WriteIR(0x3F);      // Bypass
  JTAG_WriteClocks(10);
  //
  // Configure JTAG chain, so J-Link knows to which devices it has to "talk" to.
  // CPU core is in scan chain now, so we have to re-configure the JTAG chain settings.
  // The CPU core is device 0 (closest to TDO).
  //
  JTAG_IRPre=0;
  JTAG_DRPre=0;
  JTAG_IRPost=6;
  JTAG_DRPost=1;
  JTAG_IRLen=4;
  CPU=CORTEX_A8;
  JTAG_AllowTAPReset=0; 
  //
  // Check core ID
  //
  JTAG_StoreIR(0xE);  // Read JTAG-DP IDCODE register
  v = 0;
  BitPos = JTAG_StoreDR(v, 32);         // Get ID = 0x12?
  DPIdCode = JTAG_GetU32(BitPos);       // 0x3BA00477

  if (((DPIdCode & 0x00000FFF) != 0x0000002F) && ((DPIdCode & 0x00000FFF) != 0x00000477)) {
    MessageBox1("Can not find Cortex-A8 (IDCODE mismatch), found: ", DPIdCode);
    return 1;
  }
  //
  // Check JTAG-DP IDCODE
  //
  JTAG_StoreIR(0xE);  // Read JTAG-DP IDCODE register
  BitPos = JTAG_StoreDR(0x00000000, 32);  // Get ID
  v = JTAG_GetU32(BitPos);
  if ((v & 0xFFF) != 0x00000477) {
    MessageBox("Can not find JTAG-DP (IDCODE mismatch)");
  }
  
  return 0;
}

ohnail

Beginner

Date of registration: Feb 9th 2012

Posts: 24

5

Saturday, February 11th 2012, 2:55am

C/C++ Source code

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/*********************************************************************
*
*       _SetBP
*/
void _SetBP(void) {
  __int64 Ctrl;
  //
  // Select & setup APB-AP
  //
  _StoreSelDP();
  _StoreWriteAPDPReg(2, (1 << 24) | (0 << 4));  // Select AP[1], bank 0
  _StoreSelAP();
  Ctrl =  0
       | (2 << 0)    // AP-access size. Fixed to 2: 32-bit
       | (1 << 4)    // Auto increment TAR after read/write access. Increment is NOT performed on access to banked data registers 0-3.
       | (1 << 31)   // Enable software access to the Debug APB bus.
       ;
  _StoreWriteAPDPReg(0, Ctrl);
  //
  // Step 1. Disable the breakpoint being set.
  //
  _StoreWriteAPDPReg(1, 0x54011000 + (0x50 << 2));
  _StoreWriteAPDPReg(3, 0x00000000);
  //
  // Step 2. Write address to the BVR, leaving the bottom 2 bits zero.
  //
  _StoreWriteAPDPReg(1, 0x54011000 + (0x40 << 2));
  _StoreWriteAPDPReg(3, 0x00014000);
  //
  // Step 3. Write the mask and control register to enable the breakpoint.
  //
  _StoreWriteAPDPReg(1, 0x54011000 + (0x50 << 2));
  _StoreWriteAPDPReg(3, 7 | (0xF << 5) | (0 << 20));
  JTAG_WriteClocks(1);   // Make sure that JTAG buffers are empty and breakpoint is set
}

/*********************************************************************
*
*       ResetTarget
*/
void ResetTarget(void) {
  int Speed;
  int BitPos;
  int Ctrl;
  __int64 v;

  Report("J-Link script: Reset");
  Speed = JTAG_Speed;
  JTAG_Speed = 100;
  //
  // Set breakpoint to halt target as fast as possible after reset
  //
  _SetBP();
  //
  // Setup JTAG config to "talk" to the ICEPick, so we can use the JTAG API functions
  //
  JTAG_DRPre  = 1;
  JTAG_DRPost = 0;
  JTAG_IRPre  = 4;
  JTAG_IRPost = 0;
  JTAG_IRLen  = 6;
  //
  // Perform reset via ICEPick system control register, by setting the SysReset bit
  //
  JTAG_StoreIR(2);                        // Cmd: ROUTER
  v = 0x01000000;                         // Read SYS_CNTL
  JTAG_StoreDR(v, 32);           // Send read register command
  BitPos = JTAG_StoreDR(v, 32);  // Shift out register content
  v = JTAG_GetU32(BitPos);
  v &= 0x00FFFFFF;
  v |= 0x81000001;                        // Write SYS_CNTL and set SysReset bit
  JTAG_StoreDR(v, 32);
  JTAG_WriteClocks(10);                   // The reset needs some time to get active
  //
  // Setup JTAG config to "talk" to the Cortex-R4 again
  //
  JTAG_DRPre  = 0;
  JTAG_DRPost = 1;
  JTAG_IRPre  = 0;
  JTAG_IRPost = 6;
  JTAG_IRLen  = 4;
  //
  // Check if CPU is halted. If not, halt it.
  // Select & setup APB-AP
  //
  _StoreSelDP();
  _StoreWriteAPDPReg(2, (1 << 24) | (0 << 4));  // Select AP[1], bank 0
  _StoreSelAP();
  Ctrl =  0
       | (2 << 0)    // AP-access size. Fixed to 2: 32-bit
       | (1 << 4)    // Auto increment TAR after read/write access. Increment is NOT performed on access to banked data registers 0-3.
       | (1 << 31)   // Enable software access to the Debug APB bus.
       ;
  _StoreWriteAPDPReg(0, Ctrl);
  //
  // Read DSCR to check if CPU is halted
  //
  _StoreWriteAPDPReg(1, 0x54011000 + (0x22 << 2));
  _StoreTriggerReadAPDPReg(3);
  _StoreSelDP();
  BitPos = _StoreTriggerReadAPDPReg(3);
  v = JTAG_GetU32(BitPos + 3);
  _StoreSelAP();
  if ((v & 1) == 0) {
    //
    // If CPU did not halt after reset, halt it
    //
    Report("J-Link script: Core did not halt after reset. Halting core...");
    v |= (1 << 14);
    _StoreWriteAPDPReg(1, 0x54011000 + (0x22 << 2));   // Enable debug halt mode by writing the DSCR
    _StoreWriteAPDPReg(3, v);
    _StoreWriteAPDPReg(1, 0x54011000 + (0x24 << 2));   // Write DRCR to halt CPU
    _StoreWriteAPDPReg(3, 1);
    JTAG_WriteClocks(1);
  }
  //
  // Remove breakpoint
  //
  _StoreWriteAPDPReg(1, 0x54011000 + (0x50 << 2));
  _StoreWriteAPDPReg(3, 0);
  _StoreSelDP();
  JTAG_WriteClocks(1);
  JTAG_Speed = Speed;
  
}

/*********************************************************************
*
*       InitEMU
*/
void InitEMU(void) {
  EMU_ETB_IsPresent = 0;
}

/*********************************************************************
*
*       InitTarget
*/
void InitTarget(void) {
  int v;

  Report("TI AM3359 (Cortex-A8 core) J-Link script");
  //
  // By performing a TRST reset, we make sure that only the ICEPick module is in the scan chain
  //
  JTAG_TRSTPin = 0;
  SYS_Sleep(50);
  JTAG_TRSTPin = 1;
  SYS_Sleep(50);
  JTAG_Write(0x1F, 0, 6);
  _InitIcePick();
}

ohnail

Beginner

Date of registration: Feb 9th 2012

Posts: 24

6

Monday, February 20th 2012, 4:50pm

Hi Alex,

Any thing update? ?(

Ohnail
2012.2.20

ohnail

Beginner

Date of registration: Feb 9th 2012

Posts: 24

7

Friday, March 2nd 2012, 2:38pm

Keep waiting... ;(

SEGGER - Alex

Super Moderator

Date of registration: Dec 18th 2007

Posts: 1,516

8

Friday, March 2nd 2012, 3:38pm

For clarification: This is NOT a support forum where you have a claim to get a solution in a specified time.
This is a user forum where the main intention is to get help from other users...

We are still working on AM335x support.


Best regards
Alex

miga71

Beginner

Date of registration: Apr 16th 2012

Posts: 2

9

Monday, April 16th 2012, 2:17pm

For clarification: This is NOT a support forum where you have a claim to get a solution in a specified time.
This is a user forum where the main intention is to get help from other users...
We are still working on AM335x support.
Sorry, but it is really unsatisfying that there's still no support for the am335x devices, and no news since more than a month.
We recently purchased the J-Link Ultra, together with your "J-Link TI-20-CTI Adapter". Since you offer this combination especially for the am335x evaluation board from TI on your web site, it should be ok to claim for support, or at least to ask for workarounds, otherwise other customers could also run into that pitfall.

Is there any trick or workaround we could use to get the J-Link running together with the TI eval board?

SEGGER - Alex

Super Moderator

Date of registration: Dec 18th 2007

Posts: 1,516

10

Thursday, April 19th 2012, 6:37pm

Hello all,

We have built a new beta version (V4.47a) which supports the AM335x.
For more information about some special handling required for this device, please refer to UM08001, chapter "device specifics".

Quoted

Sorry, but it is really unsatisfying that there's still no support for the am335x devices, and no news since more than a month.
We recently purchased the J-Link Ultra, together with your "J-Link TI-20-CTI Adapter". Since you offer this combination especially for the am335x evaluation board from TI on your web site, it should be ok to claim for support, or at least to ask for workarounds, otherwise other customers could also run into that pitfall.

We have not announced support for the AM335x series CPUs before V4.47a. We only announced the availability of an adapter for the TI 20-CTI connector.
I agree that the AM335x EVM was not the best example but having this as an example for a board with such a connector on it does not automatically imply having support for it ready yet.


Best regards
Alex

ohnail

Beginner

Date of registration: Feb 9th 2012

Posts: 24

11

Friday, April 20th 2012, 1:37pm

Hi Alex,

Thanks a lot for your hard work!

Ohnail

miga71

Beginner

Date of registration: Apr 16th 2012

Posts: 2

12

Tuesday, September 4th 2012, 9:19pm

Debugging AM335x with CodeSourcery CodeBench and "native" J-Link support

We are using CodeSourcery CodeBench (20012.03-69), and succeeded to debug our own board (which is very similar to the TI AM335xEVM) with the "native" J-Link support from CodeBench debug sprite.
In order to get this setup to work, we have to use a jlink settings file for the DLL, which we can specify in the debug settings. Within that file, we then force the DLL to use the AM3359 device.
Additionally, we added the board initialization code (clocks, memroy etc.) to the board.xml file from CodeBench.

So far, so good, starting a debug session and downloading code to external RAM works, but unfortunately the download speed is very poor, since the J-LINK DLL (V4.52c) always selects 1000KHz JTAG speed.

1) Is there any way in the DLL settings file to force a faster JTAG speed, or any other options to speed up JTAG?

2) We already tried to use a JLINK sript (specified in the DLL settings file), but that didn't work at all (modifying "InitTarget" and "ResetTarget" seems to destroy the recognition of the AM3359). Is it possible to get a suitable JLinkScript for the AM3359?

3) Is it a good idea to use the board.xml for the board setup, or would it be better to use an equivalent JLinkScript (which we do not have so far, see 2)?

Any help is very appreciated.

Date of registration: Oct 2nd 2012

Posts: 2

Location: Dornbirn

Occupation: Software engineer

13

Tuesday, October 2nd 2012, 5:17pm

Hello all,

We have built a new beta version (V4.47a) which supports the AM335x.
For more information about some special handling required for this device, please refer to UM08001, chapter "device specifics".

Quoted

Sorry, but it is really unsatisfying that there's still no support for the am335x devices, and no news since more than a month.
We recently purchased the J-Link Ultra, together with your "J-Link TI-20-CTI Adapter". Since you offer this combination especially for the am335x evaluation board from TI on your web site, it should be ok to claim for support, or at least to ask for workarounds, otherwise other customers could also run into that pitfall.

We have not announced support for the AM335x series CPUs before V4.47a. We only announced the availability of an adapter for the TI 20-CTI connector.
I agree that the AM335x EVM was not the best example but having this as an example for a board with such a connector on it does not automatically imply having support for it ready yet.


Best regards
Alex
I don't see this AM335x when I open JFlashARM, and I am using version 4.54a.
When I chose option "Device" in "Project settings" window, I can see for TI processors AM3505 and AM3517, but not AM335x.
So, is it possible (and how) to download firmware using Segget J-Link Pro to AM3352?

SEGGER - Alex

Super Moderator

Date of registration: Dec 18th 2007

Posts: 1,516

14

Thursday, October 4th 2012, 2:48pm

Hello,

Where(!) do you want to download the firmware to?
The AM3352 does not provide internal flash, so do you want to program external CFI NOR flash or NAND flash?
In case of NAND flash: This requires a so-called custom RAMCode since there is no generic way of supporting NAND flash since the user is free to connect it to an available NAND flash controller or to almost any GPIO pins on the device.


Best regards
Alex

Date of registration: Oct 2nd 2012

Posts: 2

Location: Dornbirn

Occupation: Software engineer

15

Thursday, October 4th 2012, 5:26pm

Hello,

Where(!) do you want to download the firmware to?
The AM3352 does not provide internal flash, so do you want to program external CFI NOR flash or NAND flash?
In case of NAND flash: This requires a so-called custom RAMCode since there is no generic way of supporting NAND flash since the user is free to connect it to an available NAND flash controller or to almost any GPIO pins on the device.


Best regards
Alex
Hello,

We have custom RamCode for flashing NAND.
Problem is that I we don't see the Segger project setup for am335x!
How can load RamCode to RAM?!

Best regards,
Strahinja

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