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jjkkty

Beginner

Date of registration: Feb 16th 2016

Posts: 6

1

Wednesday, February 17th 2016, 8:42am

[SOLVED] Getting jlink debug SAME70 with a Bootloader

Hello,I am using a jlink(sam-ice) to debug a SAME70.I want to use jlink to debug it,but I have a bootloader in it.When I click debug in Keil,jlink jump to 0x40000 where is my bootloader begins instead of where is my application's address.According to mannal(UM08001),it seems I can debug from and address by creating a "jlink script".But I didn't found
any example about CORTEX-M core.Can you give me an example (SAME70 if possible) of CORTEX-M .Is there any tutorial about how to write the "ResetTaget" function in jlink script?


Best regards :)

SEGGER - Niklas

Super Moderator

Date of registration: Oct 6th 2014

Posts: 1,691

2

Wednesday, February 17th 2016, 10:02am

Hi,


do I understand you correctly that you do not just want to execute the bootloader and then set a break point in the main program, but
instead want to jump directly to the start address of your main application after a reset?

You need to pass a J-Link Script file witch contains a ResetTarget() function in order to override the default behavior.

C/C++ Source code

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/*********************************************************************
*
*       ResetTarget
*/
void ResetTarget(void) {
  //
  //  Insert desired reset behavior here
  // 
}


Examples scripts are shipped with the J-Link software package. They be found in _JLinkInstallDir_\Samples\JLink\Scripts
e.g. Renesas_RZG1M_ConnectCore0.JLinkScript

C/C++ Source code

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/*********************************************************************
*
*       ResetTarget
*/
void ResetTarget(void) {
  int v;
  int Speed;
  int Ctrl;

  Report("******************************************************");
  Report("J-Link script: ResetTarget()");
  Report("******************************************************");
  Speed = JTAG_Speed;
  JTAG_Speed = 100;
  JTAG_WriteClocks(1);

  //
  // Select APB-AP and prepare control register
  //
  JLINK_CORESIGHT_WriteDP(2, (1 << 24) | (0 << 4));  // Select AP[1], bank 0
  Ctrl =  0
       | (2 << 0)    // AP-access size. Fixed to 2: 32-bit
       | (1 << 4)    // Auto increment TAR after read/write access. Increment is NOT performed on access to banked data registers 0-3.
       | (1 << 31)   // Enable software access to the Debug APB bus.
       ;
  JLINK_CORESIGHT_WriteAP(0, Ctrl);
  //
  // Perform some other init steps which are required to get full control of the debug logic
  //
  JLINK_CORESIGHT_WriteAP(1, 0x800B0000 + 0xFB0);
  JLINK_CORESIGHT_WriteAP(3, 0xC5ACCE55);
  JLINK_CORESIGHT_WriteAP(1, 0x800B0000 + 0x310);
  JLINK_CORESIGHT_WriteAP(3, 1);
  JLINK_CORESIGHT_WriteAP(1, 0x800B0000 + 0x314);
  JLINK_CORESIGHT_ReadAP(3);

  v = JLINK_CORESIGHT_ReadDP(3);
  //
  // Read & modify DSCR in order to enable debug halt mode
  //
  JLINK_CORESIGHT_WriteAP(1, 0x800B0000 + 0x88);
  JLINK_CORESIGHT_ReadAP(3);
  v = JLINK_CORESIGHT_ReadDP(3);
  v |= (1 << 14);
  JLINK_CORESIGHT_WriteAP(1, 0x800B0000 + 0x88);   // Enable debug halt mode by writing the DSCR
  JLINK_CORESIGHT_WriteAP(3, v);
  //
  // Halt CPU by writing the halt request bit in the DRCR
  //
  JLINK_CORESIGHT_WriteAP(1, 0x800B0000 + 0x90);
  JLINK_CORESIGHT_WriteAP(3, 1);
  JTAG_WriteClocks(1);
  JTAG_Speed = Speed;
}


Currently, there are no function to read / write CPU registers directly. You need to use the JLINK_CORESIGHT functions in order to change the value of the PC.

Best regards,
Niklas
Would you like to be added to the J-Link software update notification list, so you get informed automatically when a new version becomes available?
Just write me a PM or in case you want to subscribe to it yourself, please use this link: Link
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jjkkty

Beginner

Date of registration: Feb 16th 2016

Posts: 6

3

Thursday, February 18th 2016, 8:01am

Yes,I've read this example but still don't know how to write the reset function because all of your examples are about cortex-A but no cortex-m core.The reset behavior has a lots of differences among them and I have no idea how to write the reset function so I am here to find out is there any further information about it.







Best regards

jjkkty

Beginner

Date of registration: Feb 16th 2016

Posts: 6

4

Thursday, February 18th 2016, 8:01am

Yes,I've read this example but still don't know how to write the reset function because all of your examples are about cortex-A but no cortex-m core.The reset behavior has a lots of differences among them and I have no idea how to write the reset function so I am here to find out is there any further information about it.


Best regards

SEGGER - Niklas

Super Moderator

Date of registration: Oct 6th 2014

Posts: 1,691

5

Thursday, February 18th 2016, 4:54pm

Hi,

I prepared an example script file for STM32F4 devices:

C/C++ Source code

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/*********************************************************************
*
*       Peripherals
*/
// #define AIRCR_ADDR        0xE000ED0C 
// #define DHCSR_ADDR        0xE000EDF0
// #define DEMCR_ADDR        0xE000EDFC

/*********************************************************************
*
*       AHBAP registers
*/
// #define AHBAP_REG_CTRL    0
// #define AHBAP_REG_ADDR    1
// #define AHBAP_REG_DATA    3

/*********************************************************************
*
*       DP / AP registers
*/
// #define DP_REG_SELECT     2
/*********************************************************************
*
*       ResetTarget()
* Reset and wait until CPU is halted.
*/
void ResetTarget(void) {
  int AIRCR_ADDR     ;
  int DHCSR_ADDR     ;
  int DEMCR_ADDR     ;
  int AHBAP_REG_CTRL ;
  int AHBAP_REG_ADDR ;
  int AHBAP_REG_DATA ;
  int DP_REG_SELECT  ;
  AIRCR_ADDR         = 0xE000ED0C;
  DHCSR_ADDR         = 0xE000EDF0;
  DEMCR_ADDR         = 0xE000EDFC;
  AHBAP_REG_CTRL     = 0;
  AHBAP_REG_ADDR     = 1;
  AHBAP_REG_DATA     = 3;
  DP_REG_SELECT      = 2;


  int Ctrl;
  int demcr;
  int v;
  int Tries;
  int Done;

  if (MAIN_ActiveTIF == JLINK_TIF_JTAG) {
    JLINK_CORESIGHT_Configure("IRPre=0;DRPre=0;IRPost=0;DRPost=0;IRLenDevice=4");
  } else {
    JLINK_CORESIGHT_Configure(""); // For SWD, no special setup is needed, just output the switching sequence
  }
  //
  // Power-up complete DAP
  //
  Ctrl = 0
       | (1 << 30)     // System power-up
       | (1 << 28)     // Debug popwer-up
       | (1 << 5)      // Clear STICKYERR
       ;
  JLINK_CORESIGHT_WriteDP(1, Ctrl);
  //
  // Select AHB-AP and configure it 
  //
  JLINK_CORESIGHT_WriteDP(DP_REG_SELECT,  (0 << 4) | (0 << 24));                                     // Select AP[0] (AHB-AP) bank 0
  JLINK_CORESIGHT_WriteAP(AHBAP_REG_CTRL, (1 << 4) | (1 << 24) | (1 << 25) | (1 << 29) | (2 << 0));  // Auto-increment, Private access, HMASTER = DEBUG, Access size: word
 
  JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DHCSR_ADDR);
  v = JLINK_CORESIGHT_ReadAP(AHBAP_REG_DATA);
  v &= 0x3F;                   // Mask out "debug" bits
  v |= 0xA05F0000;             // Debug key to make a write to the DHCSR a valid one
  v |= 0x00000002;             // Halt the core
  v |= 0x00000001;             // Enable debug functionalities of the core
  JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DHCSR_ADDR);
  JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, v);
  //
  // Set VC_CORERESET
  //
  JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DEMCR_ADDR);
  demcr = JLINK_CORESIGHT_ReadAP(AHBAP_REG_DATA);
  JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DEMCR_ADDR);
  JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, demcr | 0x00000001);
  //
  // SYSRESETREQ
  //
  JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, AIRCR_ADDR);
  JLINK_CORESIGHT_WriteAP(AHBAP_REG_DATA, 0x05FA0004);
  //
  // Wait until CPU is halted
  //
  Tries = 0;
  Done  = 0;
  do {
    JLINK_CORESIGHT_WriteAP(AHBAP_REG_ADDR, DHCSR_ADDR);
    v = JLINK_CORESIGHT_ReadAP(AHBAP_REG_DATA);
    //
    // Check if CPU is halted. If so, we are done
    //
    if (Tries >= 5) {
      MessageBox("STM32 (connect): Timeout while waiting for CPU to halt after reset. Manually halting CPU.");
      Done = 1;
    }
    if (v & 0x00020000) { // 1 << 17
      Done = 1;
    }
    Tries = Tries + 1;
    SYS_Sleep(100);
  } while(Done == 0);
}


Please note that you may need to adjust this example in order to use it with SAME70.

Best regards,
Niklas
Would you like to be added to the J-Link software update notification list, so you get informed automatically when a new version becomes available?
Just write me a PM or in case you want to subscribe to it yourself, please use this link: Link
Notification for J-Link, J-Link Debugger, SystemView & J-Scope: Link
Notification for Embedded Studio: Link

jjkkty

Beginner

Date of registration: Feb 16th 2016

Posts: 6

6

Friday, February 19th 2016, 5:42am

Thanks for the script!It seems work since the chip reset with script acts like it uses a default reset define by the DLL.
But when I use "CORESIGHT_CoreBaseAddr" variables to control where the program starts,it didn't work.What's the problem in it?

jjkkty

Beginner

Date of registration: Feb 16th 2016

Posts: 6

7

Friday, February 19th 2016, 8:18am

According to the UM08001 the "CORESIGHT_CoreBaseAddr" should be R/W but when I try to print it by function "Report1",it shows "Error while parsing script file .... Variable is write-only".Is it write-only or I shouldn't print it by "Report1"?

SEGGER - Niklas

Super Moderator

Date of registration: Oct 6th 2014

Posts: 1,691

8

Friday, February 19th 2016, 9:25am

Hi,


I could reproduce this issue.
I will check whether this is an documentation or implementation issue.


Best regards,
Niklas
Would you like to be added to the J-Link software update notification list, so you get informed automatically when a new version becomes available?
Just write me a PM or in case you want to subscribe to it yourself, please use this link: Link
Notification for J-Link, J-Link Debugger, SystemView & J-Scope: Link
Notification for Embedded Studio: Link

jjkkty

Beginner

Date of registration: Feb 16th 2016

Posts: 6

9

Friday, February 19th 2016, 9:31am

Hi,


Did you reproduce "Report1" or can no change base address problem?
The change base address one is more urgent !

SEGGER - Niklas

Super Moderator

Date of registration: Oct 6th 2014

Posts: 1,691

10

Friday, February 19th 2016, 11:59am

Hi,


CORESIGHT_CoreBaseAdd is not the variable you are looking for:

Quoted

Sets base address of core debug component for
CoreSight compliant devices. Setting this vari-
able disables the J-Link auto-detection of the
core debug component base address. Used on
devices where auto-detection of the core debug
component base address is not possible due to
incorrect CoreSight information.


Currently, we can not provide an example for setting the PC by using CoreSight.
Convenience functions like SetPC() are planned for a future release of the J-Link software & documentation pack, but without a fixed release yet.
Until then, you need either to consult the CoreSight Components manual and the reference manual of the AtSAME70 or stick with a simpler solution, e.g. removing the bootloader temporary and directly start with the application.

Best regards,
Niklas
Would you like to be added to the J-Link software update notification list, so you get informed automatically when a new version becomes available?
Just write me a PM or in case you want to subscribe to it yourself, please use this link: Link
Notification for J-Link, J-Link Debugger, SystemView & J-Scope: Link
Notification for Embedded Studio: Link